Talk:ASUS RT-N11P B1

GPL info

 * http://forum.ixbt.com/topic.cgi?id=14:63903:3061#3061
 * https://github.com/Linaro1985/padavan-ng/tree/master/trunk/configs/boards/ASUS

export RT-N300_BASE := IPV6SUPP=y HTTPS=y MIPS32=r2 RALINK=y MT7628=y SSH=y EBTABLES=y PARENTAL2=y ACCEL_PPTPD=y VPNC=y SHP=y RTN11PB1=y ODMPID=y NEW_RGDM=y RA_SKU=y REPEATER=y RA_SKU_IN_DRV=y TCODE=y MDNS=y FINDASUS=y BTN_WPS_RST=y DISABLE_NETWORKMAP=n WAN_AT_P4=y LANWAN_LED=y BLINK_LED=y SINGLE_2G=y YANDEXDNS=y NEW_USER_LOW_RSSI=y AUTODICT=y REDIRECT_DNAME=y LAN50=y BTN_WPS_ALLLED=y NEWSSID_REV2=y ATCOVER=y GETREALIP=y REBOOT_SCHEDULE=y \ EDCCA_NEW=y \ TEMPROOTFS=y \ BOOT_FLASH_TYPE=SPI \ DRAM=32M

export RT-N11P_B1 := $(RT-N300_BASE) export RT-N11P_B1 += BUILD_NAME="RT-N11P_B1" EXTRA_KERNEL_CONFIGS="MT7628_BAUDRATE=57600 RT2880_DRAM_32M=y       UBOOT_CMDLINE=y MODEL_RTN11PB1=y SHRINK_PAGECACHE=y"

export RT-N10P_V3 := $(RT-N300_BASE) export RT-N10P_V3 += BASE_MODEL="RT-N11P_B1" BUILD_NAME="RT-N10P_V3" EXTRA_KERNEL_CONFIGS="MT7628_BAUDRATE=57600 RT2880_DRAM_32M=y       UBOOT_CMDLINE=y MODEL_RTN10PV3=y SHRINK_PAGECACHE=y"

 /* ASUS RT-N11P B1 */


 * 1) define BOARD_PID		"RT-N11PB1"
 * 2) define BOARD_NAME		"RT-N11P_B1"
 * 3) define BOARD_DESC		"ASUS RT-N11P B1 Wireless Router"
 * 4) define BOARD_VENDOR_NAME	"ASUSTek Computer Inc."
 * 5) define BOARD_VENDOR_URL	"http://www.asus.com/"
 * 6) define BOARD_MODEL_URL		"http://www.asus.com/Networking/RT-N11P-B1/"
 * 7) define BOARD_BOOT_TIME		20
 * 8) define BOARD_FLASH_TIME	90
 * 9) define BOARD_GPIO_BTN_RESET	5
 * 10) undef BOARD_GPIO_BTN_WPS
 * 11) undef BOARD_GPIO_LED_ALL
 * 12) define BOARD_GPIO_LED_WIFI	44
 * 13) define BOARD_GPIO_LED_POWER	37
 * 14) define BOARD_GPIO_LED_LAN	42
 * 15) define BOARD_GPIO_LED_WAN	43
 * 16) undef BOARD_GPIO_LED_USB
 * 17) undef BOARD_GPIO_LED_ROUTER
 * 18) undef BOARD_GPIO_PWR_USB
 * 19) define BOARD_HAS_5G_11AC	0
 * 20) define BOARD_NUM_ANT_5G_TX	0
 * 21) define BOARD_NUM_ANT_5G_RX	0
 * 22) define BOARD_NUM_ANT_2G_TX	2
 * 23) define BOARD_NUM_ANT_2G_RX	2
 * 24) define BOARD_NUM_ETH_LEDS	0
 * 25) define BOARD_HAS_EPHY_L1000	0
 * 26) define BOARD_HAS_EPHY_W1000	0


 * 1) Board PID    # Board Name         # PRODUCT # Note
 * 2) RT-N11P_B1   # ASUS RT-N11P B1    # MT7628  #
 * 1) RT-N11P_B1   # ASUS RT-N11P B1    # MT7628  #
 * 1) RT-N11P_B1   # ASUS RT-N11P B1    # MT7628  #

CFLAGS += -DBOARD_N11PB1 -DVENDOR_ASUS BOARD_NUM_USB_PORTS=0

\asuswrt\release\src\router\rc\init.c
case MODEL_RTN11P_B1: nvram_set("boardflags", "0x100"); // although it is not used in ralink driver, set for vlan nvram_set("vlan1hwname", "et0"); // vlan. used to get "%smacaddr" for compare and find parent interface. nvram_set("vlan2hwname", "et0"); // vlan. used to get "%smacaddr" for compare and find parent interface. nvram_set("lan_ifname", "br0"); //set_basic_ifname_vars("vlan2", "vlan1", "ra0", "rai0", "usb", "vlan1", NULL, "vlan3", 0); set_basic_ifname_vars("vlan2", "vlan1", "ra0", NULL, NULL, "vlan1", NULL, "vlan3", 0); nvram_set_int("btn_rst_gpio", 5|GPIO_ACTIVE_LOW); nvram_set_int("btn_wps_gpio", 5|GPIO_ACTIVE_LOW); nvram_set_int("led_wan_gpio", 43|GPIO_ACTIVE_LOW); nvram_set_int("led_lan_gpio", 42|GPIO_ACTIVE_LOW); nvram_set_int("led_wps_gpio", 44|GPIO_ACTIVE_LOW); nvram_set_int("led_pwr_gpio", 37|GPIO_ACTIVE_LOW); nvram_set_int("led_2g_gpio", 44|GPIO_ACTIVE_LOW); /* enable bled */ config_swports_bled("led_wan_gpio", 0); config_swports_bled("led_lan_gpio", 0); //eval("rtkswitch", "11"); nvram_set("ct_max", "1024"); // force if (nvram_get("wl_mssid") && nvram_match("wl_mssid", "1")) add_rc_support("mssid"); add_rc_support("2.4G update"); add_rc_support("rawifi"); //add_rc_support("switchctrl"); add_rc_support("manual_stb"); //add_rc_support("11AC"); //either txpower or singlesku supports rc. add_rc_support("pwrctrl"); // the following values is model dep. so move it from default.c to here nvram_set("wl0_HT_TxStream", "2"); nvram_set("wl0_HT_RxStream", "2"); //nvram_set("wl1_HT_TxStream", "2"); //nvram_set("wl1_HT_RxStream", "2"); break;
 * 1) if defined(RTN11P_B1)
 * 1) endif /* RTN11P_B1 */

\asuswrt\release\src-ra-4300\Uboot\config_n11pb1
CONFIG_CROSS_COMPILER_PATH="/opt/buildroot-gcc342/bin" CONFIG_ASUS_PRODUCT=y CONFIG_RTN11PB1=y RELOAD_N=y ASIC_BOARD=y MT7628_ASIC_BOARD=y MT7628_MP=y P5_MAC_TO_NONE_MODE=y P4_MAC_TO_NONE_MODE=y ON_BOARD_SPI_FLASH_COMPONENT=y ON_BOARD_DDR1=y ON_BOARD_256M_DRAM_COMPONENT=y ON_BOARD_DDR_WIDTH_16=y ON_BOARD_16BIT_DRAM_BUS=y UBOOT_ROM=y MT7628_CPU_PLL_PARAMETERS=y CPUCLK_FROM_CPLL=y CPU_FRAC_DIV=0x1 TEXT_BASE=0xBC000000 LAN_WAN_PARTITION=y RALINK_EV_BOARD_PVLAN=y ALL_LED_OFF_RXD_GPIONR4=y
 * 1) Automatically generated by make menuconfig: don't edit
 * 1) Automatically generated by make menuconfig: don't edit
 * 1) CONFIG_RALINK_PRODUCT is not set
 * 1) RELOAD_Y is not set
 * 1) RT2880_ASIC_BOARD is not set
 * 2) RT3350_ASIC_BOARD is not set
 * 3) RT3052_ASIC_BOARD is not set
 * 4) RT3352_ASIC_BOARD is not set
 * 5) RT3883_ASIC_BOARD is not set
 * 6) RT5350_ASIC_BOARD is not set
 * 7) RT6855A_ASIC_BOARD is not set
 * 8) MT7620_ASIC_BOARD is not set
 * 9) MT7621_ASIC_BOARD is not set
 * 1) ON_BOARD_DDR2 is not set
 * 2) ON_BOARD_DDR3 is not set
 * 1) ON_BOARD_512M_DRAM_COMPONENT is not set
 * 2) ON_BOARD_1024M_DRAM_COMPONENT is not set
 * 3) ON_BOARD_2048M_DRAM_COMPONENT is not set
 * 4) ON_BOARD_DDR_WIDTH_8 is not set
 * 1) UBOOT_RAM is not set
 * 1) CPUCLK_FROM_BPLL is not set
 * 2) CPUCLK_FROM_XTAL is not set
 * 1) DUAL_IMAGE_SUPPORT is not set
 * 1) RALINK_DEMO_BOARD_PVLAN is not set
 * 1) ALL_LED_OFF_NONE is not set

\asuswrt\release\src-ra-4300\Uboot\config.in
if [ "$MT7628_FPGA_BOARD" = "y" -o "$MT7628_ASIC_BOARD" = "y" ]; then define_bool MT7628_MP y
 * 1) MT7628
 * 1) MT7628

define_bool P5_MAC_TO_NONE_MODE y define_bool P4_MAC_TO_NONE_MODE y
 * 1) MT7628 GMAC
 * 1) MT7628 GMAC

define_bool ON_BOARD_SPI_FLASH_COMPONENT y
 * 1) MT7628 FLASH
 * 1) MT7628 FLASH

if [ "$DUAL_IMAGE_SUPPORT" = "y" ]; then choice 'Flash Size' "4M ON_BOARD_4M_FLASH_COMPONENT \                    8M ON_BOARD_8M_FLASH_COMPONENT \                     16M ON_BOARD_16M_FLASH_COMPONENT                    " 4M fi choice 'DRAM Type' "DDR1 ON_BOARD_DDR1 \                   DDR2 ON_BOARD_DDR2                    "DDR2
 * 1) MT7628 DRAM
 * 1) MT7628 DRAM

if [ "$ON_BOARD_SDR" = "y" ]; then choice 'DRAM Component' "64Mb ON_BOARD_64M_DRAM_COMPONENT \                        128Mb ON_BOARD_128M_DRAM_COMPONENT \                         256Mb ON_BOARD_256M_DRAM_COMPONENT \                         512Mb ON_BOARD_512M_DRAM_COMPONENT                      " 128Mb else if [ "$ON_BOARD_DDR1" = "y" ]; then choice 'DDR Component' "128Mb ON_BOARD_128M_DRAM_COMPONENT \                         256Mb ON_BOARD_256M_DRAM_COMPONENT \                          512Mb ON_BOARD_512M_DRAM_COMPONENT \                          1024Mb ON_BOARD_1024M_DRAM_COMPONENT                       " 256Mb else if [ "$ON_BOARD_DDR2" = "y" ]; then choice 'DDR Component' "256Mb ON_BOARD_256M_DRAM_COMPONENT \                          512Mb ON_BOARD_512M_DRAM_COMPONENT \                           1024Mb ON_BOARD_1024M_DRAM_COMPONENT \                           2048Mb ON_BOARD_2048M_DRAM_COMPONENT                        " 512Mb fi fi fi

if [ "$ON_BOARD_DDR1" = "y" -o "$ON_BOARD_DDR2" = "y" ]; then choice 'DDR Width' "8bits ON_BOARD_DDR_WIDTH_8 \                   16bits ON_BOARD_DDR_WIDTH_16                   " 16bits fi

define_bool ON_BOARD_16BIT_DRAM_BUS y comment "" choice 'Ram/Rom version' "RAM UBOOT_RAM \                         ROM UBOOT_ROM                         " ROM define_bool MT7628_CPU_PLL_PARAMETERS y if [ "$MT7628_CPU_PLL_PARAMETERS" = "y" ]; then choice 'CPU clock source' "CPLL CPUCLK_FROM_CPLL  \                                   BPLL CPUCLK_FROM_BPLL \                                   XTAL CPUCLK_FROM_XTAL                                 " CPLL define_bool    CPUCLK_FROM_CPLL               y        define_hex      CPU_FRAC_DIV                    0x1 hex "Fractional divider for clock source (0x1~0xA)" CPU_FRAC_DIV 0x1 else define_bool    CPUCLK_FROM_CPLL               y     define_hex     CPU_FRAC_DIV                    0x1 fi
 * 1) MT7628 Option
 * 1) MT7628 Option
 * 1) define_bool PDMA_NEW y
 * 2) define_bool RX_SCATTER_GATTER_DMA y
 * 1) if [ "$ON_BOARD_SPI_FLASH_COMPONENT" == "y" ]; then
 * 1) choice 'Small Uboot/Config partition' "Normal_Partition_5_sectors NORMAL_UBOOT_PARTITION \
 * 2)                                      Small_Partition_3_sectors SMALL_UBOOT_PARTITION
 * 3)                                     " Normal_Partition_5_sectors
 * 4) else
 * 5) define_bool UBOOT_RAM y
 * fi
 * 1) Enable(uncomment) following line to enable the adjustment for CPU PLL settings in menuconfig,
 * 2) and then input:  make mrproper;make menuconfig
 * 1) and then input:  make mrproper;make menuconfig

SingleSKU_2.4G_FCC.dat
# |CCK 1~11 | |    OFDM 6 ~ 54      | |             HT20 MCS 0 ~ 15                 | |        HT40 MCS 0 ~ 15         | ch1 20 20 20 20 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 ch2 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 ch3 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 ch4 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ch5 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ch6 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ch7 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ch8 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ch9 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ch10 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ch11 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 ch12 20 20 20 20 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 21 21 21 21 20 20 19 19 ch13 19 19 19 19 14 14 14 14 14 14 14 14 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 ch14
 * 1) Single SKU Max Power Table
 * 1) End of Single SKU Table

MT7628_ASIC_BOARD
led_all_on; vdelay(1000000); led_all_off; vdelay(1000000); led_power_on; ifdef GPIO14_RESET_MODE RALINK_REG(RALINK_SYSCTL_BASE+0x3C)|= (1<<8); RALINK_REG(RALINK_SYSCTL_BASE+0x64)&= ~((0x3<<16)|(0x3)); /* Enable ePA/eLNA share pin */ {       char ee35, ee36; raspi_read((char *)&ee35, CFG_FACTORY_ADDR-CFG_FLASH_BASE+0x35, 1); raspi_read((char *)&ee36, CFG_FACTORY_ADDR-CFG_FLASH_BASE+0x36, 1); if ((ee35 & 0x2) || ((ee36 & 0xc) == 0xc)) {           RALINK_REG(RALINK_SYSCTL_BASE+0x60)|= ((0x3<<24)|(0x3 << 6)); }   }    // reset MIPS now also reset Andes RALINK_REG(RALINK_SYSCTL_BASE+0x38)|= 0x200; /* turn off WAN, LAN, WLAN, USB LED */ mtk7620_set_gpio_pin(WAN_LED, 1); mtk7620_set_gpio_pin(LAN_LED, 1); mtk7620_set_gpio_pin(WIFI_2G_LED, 1); mtk7620_set_gpio_pin(USB_LED, 1); mtk7620_set_gpio_pin(WIFI_2G_LED, 1); mtk7620_set_gpio_pin(USB_LED, 1); mtk7620_set_gpio_pin(WIFI_2G_LED, 1); mtk7620_set_gpio_pin(USB_LED, 1); mtk7620_set_gpio_pin(WIFI_2G_LED, 1); mtk7620_set_gpio_pin(USB_LED, 1); mtk7621_set_gpio_pin(WAN_LED, 1); mtk7621_set_gpio_pin(LAN_LED, 1); mtk7621_set_gpio_pin(WIFI_2G_LED, 1); mtk7621_set_gpio_pin(WIFI_5G_LED, 1); mtk7621_set_gpio_pin(USB_LED, 1); mtk7620_set_gpio_pin(WAN_LED, 1); mtk7620_set_gpio_pin(LAN_LED, 1); mtk7620_set_gpio_pin(WIFI_2G_LED, 1); mtk7620_set_gpio_pin(WIFI_5G_LED, 1); mtk7620_set_gpio_pin(USB_LED, 1); mtk7620_set_gpio_pin(WIFI_2G_LED, 1); mtk7620_set_gpio_pin(WAN_LED, 1); mtk7620_set_gpio_pin(LAN_LED, 1); set_gpio_pin(WIFI_2G_LED, 1); set_gpio_pin(WAN_LED, 1); set_gpio_pin(LAN_LED, 1); set_gpio_pin(WIFI_2G_LED, 1); set_gpio_pin(USB_LED, 0);
 * 1) elif defined(ASUS_RTN11PB1)
 * 1) endif
 * 1) if defined(MT7628_ASIC_BOARD) /* Enable WLED share pin */
 * 2) if !defined(ASUS_RTN11PB1)
 * 1) endif
 * 2) endif
 * 1) if defined(MT7628_ASIC_BOARD)
 * 1) endif
 * 1) ifdef ASUS_PRODUCT
 * 2) if defined(ASUS_RTN14U) || defined(ASUS_RTAC52U)
 * 1) elif defined(ASUS_RTAC51U)
 * 1) elif defined(ASUS_RTAC51UP) || defined(ASUS_RTAC53)
 * 1) elif defined(ASUS_RTN54U) || defined(ASUS_RTAC54U)
 * 1) elif defined(ASUS_RTN56UB1) || defined(ASUS_RTAC1200GA1) || defined(ASUS_RTAC1200GU)
 * 1) elif defined(ASUS_RTAC1200HP)
 * 1) elif defined(ASUS_RTN11P)
 * 1) elif defined(ASUS_RTN11PB1)
 * 1) elif defined(ASUS_RTAC1200)
 * 1) endif

ProductID
CONFIG_FIRMWARE_PRODUCT_ID="RT-N11P_B1"
 * 1) Target ProductID (board select, max 12 symbols)
 * 2) CONFIG_FIRMWARE_PRODUCT_ID="RT-N10P_V3"
 * 3) CONFIG_FIRMWARE_PRODUCT_ID="RT-N11P"
 * 1) CONFIG_FIRMWARE_PRODUCT_ID="RT-N12+"
 * 2) CONFIG_FIRMWARE_PRODUCT_ID="RT-N12+_B1"
 * 3) CONFIG_FIRMWARE_PRODUCT_ID="RT-N12+_V3"
 * 4) CONFIG_FIRMWARE_PRODUCT_ID="RT-N12E_B1"
 * 5) CONFIG_FIRMWARE_PRODUCT_ID="RT-N14U"
 * 6) CONFIG_FIRMWARE_PRODUCT_ID="RT-N300"
 * 7) CONFIG_FIRMWARE_PRODUCT_ID="RT-N300_BASE"
 * 8) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC51U"
 * 9) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC51U+"
 * 10) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC53"
 * 11) CONFIG_FIRMWARE_PRODUCT_ID="RT-N54U"
 * 12) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC54U"
 * 13) CONFIG_FIRMWARE_PRODUCT_ID="RP-AC56"
 * 14) CONFIG_FIRMWARE_PRODUCT_ID="RT-N56U"
 * 15) CONFIG_FIRMWARE_PRODUCT_ID="RT-N56UB1"
 * 16) CONFIG_FIRMWARE_PRODUCT_ID="RT-N56UB2"
 * 17) CONFIG_FIRMWARE_PRODUCT_ID="RT-N65U"
 * 18) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC85U"
 * 19) CONFIG_FIRMWARE_PRODUCT_ID="RT-N600"
 * 20) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC1200"
 * 21) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC1200HP"
 * 22) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC1200GU"
 * 23) CONFIG_FIRMWARE_PRODUCT_ID="RT-AC1200GA1"