MIPS32

MIPS32 Architecture
Imagination's MIPS32® architecture is a highly performance-efficient, industry standard architecture that is at the heart of billions of electronic products, from tiny microcontrollers to high-end networking equipment. It provides a robust instruction set, scalability from 32-bits to 64-bits, a broad-spectrum of software development tools and widespread support from numerous partners and licensees.

The MIPS32 architecture provides seamless upward compatibility to the 64-bit MIPS64® architecture, bringing powerful features, standardized privileged mode instructions, and support for past ISA versions. The MIPS32 architecture incorporates important functionality including SIMD (Single Instruction Multiple Data) and virtualization. These technologies, in conjunction with technologies such as multi-threading (MT), DSP extensions and EVA (Enhanced Virtual Addressing) enrich the architecture for use with modern software workloads which require larger memory sizes, increased computational horsepower and secure execution environments.

The MIPS32 architecture is based on a fixed-length, regularly encoded instruction set and uses a load/store data model. The architecture is streamlined to support optimized execution of high-level languages. Arithmetic and logic operations use a three-operand format, allowing compilers to optimize complex expressions formulation. Availability of 32 general-purpose registers enables compilers to further optimize code generation for performance by keeping frequently accessed data in registers.

A set of registers reflects the configuration of the caches, MMU, TLB, and other privileged features implemented in each core. By standardizing privileged mode and memory management and providing the information through the configuration registers, the MIPS32 architecture enables real-time operating systems, other development tools, and application code to be implemented once and reused with various members of both the MIPS32 and the MIPS64 processor families.

Flexibility of its high-performance caches and memory management schemes are strengths of the MIPS architecture. The MIPS32 architecture extends these advantages with well-defined cache control options. The size of the instruction and data caches can range from 256 bytes to 4 MB. The data cache can employ either a write-back or write-through policy. A no-cache option can also be specified. The memory management mechanism can employ either a TLB or a Block Address Translation (BAT) policy. With a TLB, the MIPS32 architecture meets Windows CE, Linux and Android memory management requirements.

Documentation

 * MIPS32 Architecture
 * MIPS Instruction Set Quick Reference
 * MIPS32 Instruction Set Quick Reference v1.01
 * MIPS32 Architecture for Programmers
 * Volume I: Introduction to the MIPS32 Architecture v6.01
 * Volume I-B: Introduction to the microMIPS32 Architecture v5.03
 * Volume II: The MIPS32 Instruction Set v6.02
 * Volume II-B: The microMIPS32 Instruction Set v5.04
 * Volume III: The MIPS32 and microMIPS32 Privileged Resource Architecture v5.05

MIPS32 Classic Processor Cores
MIPS32 MIPS

MIPS32 Classic Cores target every design need from entry level to high performance across embedded designs, digital consumer, broadband access and networking, and state-of-the-art communications.

MIPS32 1074Kc / 1074Kf
MIPS 1074K | MIPS 1074Kc

High performance cache coherent multiprocessor system (CPS) supporting up to four MIPS32 1074K processor cores. The 1074K CPS is based on the combination of two high-performance technologies—coherent multiprocessing, and the superscalar, multi-issue 15 stage pipeline Out-of-Order MIPS32 74K® processor core as the base CPU.

Multi-CPU coherence is enabled by a Coherence Manager Unit, a high throughput fabric supporting internal 256-bit datapaths and connection to an optional L2 cache controller. 1074K single core delivers a performance of 1.93 DMIPS/MHz and 3.49 Coremarks/MHz. The 1074Kf version includes an IEEE754 compliant Floating Point Unit, supporting both single and double precision datatypes.

Documentation

 * Boot-CPS: Example Example Boot Code for MIPS® Cores
 * MIPS32® 1074K™ Coherent Processing System Datasheet v1.03
 * MIPS32® 1074K™ CPU Family Software User's Manual v1.03

MIPS32 1004Kc / 1004Kf
MIPS 1004K | MIPS 1004Kc

High performance cache coherent multiprocessor system (CPS) supporting up to four MIPS32 1004K multi-threaded processor cores and an optional coherent I/O port. The 1004K processor core is based on a 9-stage pipeline design with support for up to two hardware threads/core. Multi-CPU coherence is enabled by a Coherence Manager Unit, which also can connect to an optional L2 cache controller with 256-bit datapath. 1004K single core delivers a performance of 1.6 DMIPS/MHz and 3.05 Coremarks/MHz. The 1004Kf version includes an IEEE754 compliant Floating Point Unit, supporting both single and double precision datatypes.

Documentation

 * The MIPS32® 1004K™ Product Brief
 * MIPS32® 1004K™ CPU Family Software User's Manual
 * MIPS32® 1004K™ Coherent Processing System Datasheet
 * Programming the MIPS32® 1004K™ Coherent Processing System Family

MIPS32 74Kc / 74Kf
MIPS 74K | MIPS 74Kc | MIPS 74Kf


 * Processor Identification: 00019740 (Processor ID: 0x97; Rev: 2.0.0)

The MIPS32 74K is based on a superscalar asymmetric dual-issue pipeline microarchitecture
 * with out-of-order (OoO) instruction dispatch and completion.

The implementation features a 15-stage pipeline to achieve high synthesizable frequencies, and
 * supports up to 4 instructions fetched per cycle, plus up to 4 instructions issued per cycle.

The 74Kc/f incorporates the MIPS DSP Module Rev2 for enhanced signal processing capabilities.

The 74Kc/f includes an OCP Bus Interface Unit and connection to an optional L2 cache controller
 * and delivers a performance of 1.93 DMIPS/MHz and 3.48 Coremarks/MHz.

The core also includes an IEEE754 compliant Floating Point Unit, supporting both single
 * and double precision datatypes.

Documentation

 * Architectural Strengths of the MIPS32 74K Core Family
 * MIPS32 74Kc Processor Core Datasheet
 * MIPS32 74Kf Processor Core Datasheet
 * Programming the MIPS32 74K Core Family
 * Programming the MIPS 74K Core Family for DSP Applications
 * MIPS32 74K Processor Core Family Software User’s Manual
 * 74K BDTi DSP White Paper
 * Breaking the Gigahertz Speed Barrier with an
 * Automated Flow Using Synopsys ICC Compiler

MIPS32 34Kc / 34Kf
MIPS 34K | MIPS 34Kc

The MIPS32 34K is a 9-stage pipeline multi-threaded processor core with support for up to two Virtual Processing Elements (VPE) and nine Thread Context (TC)s per VPE. Processing multiple software threads in parallel, 34K cores mask the effect of memory latency to deliver instant 20-40% gains in system performance and cost savings, with a very modest increase in die size.

Depending on the application, the 34K core can implement symmetric multiprocessing across two VPEs. Alternatively, each VPE can run a separate operating system. The 34Kc/f also includes an optional the MIPS DSP Module, programmable L1 cache controller and OCP Bus interface Unit. The 34K processor core delivers a performance of 1.6 DMIPS/MHz and 3.05 Coremarks/MHz. The core includes an IEEE754 compliant Floating Point Unit, supporting both single and double precision datatypes.

Documentation

 * MIPS32® 34K™ Processor Core Family Software User’s Manual
 * MIPS32® 34Kc™ Processor Core Datasheet
 * MIPS32® 34Kf™ Processor Core Datasheet
 * MIPS® MT Principles of Operation
 * Programming the MIPS32® 34K™ Core Family

MIPS32 24K / 24KE
MIPS 24K | MIPS 24Kc | MIPS 24Kf | MIPS 24KEc | MIPS 24KEf

The MIPS32 24K is a 8-stage pipeline processor core that implements the MIPS32 Release 2
 * Architecture, including support for dynamic branch prediction, optional MIPS DSP module,
 * MIPS16e Instruction Set Architecture and programmable L1 cache controller.

The 24K includes an OCP Bus Interface Unit, EJTAG debug and MIPS Trace support is provided.
 * The processor core delivers a performance of 1.6 DMIPS/MHz and 3.1 Coremarks/MHz.

The 24Kf version includes an IEEE754 compliant FPU, supporting both single and double precision datatypes.

Documentation

 * MIPS32 24K Processor Core Family Software User's Manual v3.11
 * MIPS32 24Kc Processor Core Datasheet v4.00
 * MIPS32 24Kf Processor Core Datasheet v4.00
 * Programming the MIPS32 24K Core Family v4.63
 * The MIPS32 24KE Core Family: High-Performance RISC Cores with DSP Enhancements (PDF)
 * Working with ScratchPad RAMs for MIPS32 24K and 34K Cores

MIPS32 M14K / M14Kc
MIPS M14K | MIPS M14Kc

The MIPS32 M14K family of cores have a high-performance, compact, low-power design with features that are optimized to deliver a superior solution for microcontroller (MCU) and real-time embedded system applications. The MIPS32 M14K™ family includes the MIPS32 M14K and MIPS32 M14Kc processor cores, the first MIPS32-compatible processor cores to execute the new microMIPS™ code compression Instruction Set Architecture (ISA).

The M14K core includes real time performance, flash memory acceleration, reduced interrupt latency, features required for best in class MCU designs. The core includes a programmable instruction, data cache controller and Translation Lookaside Buffer Memory Management Unit (TLB MMU), enabling high performance execution of Linux and other virtual memory operating systems. M14K processor cores deliver a performance of 1.57 DMIPS/MHz and 3.4 Coremarks/MHz.

Documentation

 * MIPS32® M14K™ Processor Core data sheet
 * MIPS32® M14K™ Processor Core Family Software User's Manual
 * MIPS32® M14Kc™ Processor Core Family Datasheet
 * MIPS32® M14Kc™ Processor Core Family Software User's Manual

MIPS32 4K / M4K / 4Kc / 4KE / 4KEc / 4KSd
MIPS 4K | MIPS 4Kc | MIPS 4KE | MIPS 4KEc

MIPS 4K / M4K
The MIPS32 M4K/4K family includes MIPS32 4K, MIPS32 4KSd, MIPS32 4KE and MIPS32 M4K
 * 32-bit synthesizable processor cores.

The MIPS32 M4K/4K family of 32-bit synthesizable core provides a highly performance-efficient, feature-rich
 * solution for a broad range of real-time, cost-sensitive embedded system applications.

Based on the well-proven MIPS Release 2 architecture, the M4K core is designed around a 5-stage pipeline,
 * SRAM interface and comprehensive debug features.

In addition, the M4K core includes the MIPS16e Application Specific Extension (ASE), reducing code size by up to 40%.
 * The M4K processor core in MIPS32 mode delivers a performance of 1.6 DMIPS/MHz and 3.4 Coremarks/MHz.

MIPS 4Kc

 * Processor Identification: 0x0001800a (Processor ID: 0x80; Maj.Rev: 0x0; Min. Rev: 0x2; Patch Level: 0x2)
 * http://www.mips.com/products/cores/hard-ip-cores/4kc-hard-ip-core/


 * - Based on MIPS32 architecture for high performance.
 * - MIPS32 4Kc hard IP core offers performance of 190 MHz and allows designers to significantly
 * reduce design time, efficiently use resources, and quickly get to market.
 * - TLB and register files arrays reduce power consumption without reducing application performance.
 * - Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging.
 * - Testability features include BIST and full scan.
 * - Support MIPS32 release 1 instructions.
 * - 8KB Instruction and 8KB Data cache.

MIPS 4KEc

 * Processor Identification(s):
 * 000184xx, e.g. 00018448
 * 000190xx alias 4KEcR2, e.g. 00019064 (Processor ID: 0x90; Maj.Rev: 0x3; Min. Rev: 0x1)


 * Datasheet:
 * https://web.archive.org/web/20160327100534/https://www.rockbox.org/wiki/pub/Main/IriverLPlayerPort/MIPS-4KEcDataSheet.pdf

"- MIPS32 Release 2 capabilities, included in version 3.0 or higher core releases"

- p. 43 in MIPS-4KEcDataSheet.pdf


 * Press Release:
 * http://www.mips.com/products/cores/hard-ip-cores/4kec-hard-ip-cores/


 * - Based on MIPS32 architecture for high performance.
 * - Hard IP cores allow designers to significantly reduce design time,
 * efficiently use resources, and quickly get to market.
 * - Instruction and data scratchpad interfaces available.
 * - 8KB Instruction and 8KB writeback Data cache for more flexibility and higher performance.
 * - A coprocessor 2 (COP2) interface enables easy coprocessor connection and support.
 * - Extensive clock gating reduces power consumption without reducing application performance.
 * - Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging.
 * - All major operating systems and compiler tool chains, and hundreds of third-party
 * development tools, support the MIPS architecture.
 * - Supports CorExtend capability which enables users to significantly enhance
 * the value and competitive advantage of their SoC products.
 * - Testability features include BIST and full scan.

Documentation

 * MIPS32 4Kc Processor Core Data Sheet
 * MIPS32 4K Processor Core Family Software User's Manual
 * MIPS32 4Km Processor Core Data Sheet
 * MIPS32 4Kp Processor Core Data Sheet