Broadcom BMIPS3300
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Info
- Processor Identification: 000290XX (Broadcom; Processor ID: 0x90; XX - Revision)
- Revision depends on:
- revision of MIPS ISA specification
- ASEs, EJTAG, FPU and their revisions.
- Major performance features.
- Physical implementations, such as custom blocks or process technologies.
- Standard MIPS32 Instruction Set Architecture (ISA)
- MIPS II ISA with extended instructions for embedded applications
- 32-bit address and data paths
- MIPS R4000 style privileged resource architecture
- MIPS R4000 exception model
- MIPS R4000 MMU with 32-entry TLB
- Odd/even page translation, variable page sizes from 4 KB to 16 MB
- Fully programmable with a set of CP0 registers and instructions
- Byte ordering of operands in either big or little endian configuration
- MIPS32 extended instructions
- MIPS16e application-specific extension
- Multiply-accumulate instructions (MADD, MADDU, MSUB, MSUBU)
- Targeted multiply instruction (MUL)
- Count leading zero and one bit-manipulation instructions (CLZ, CLO)
- Conditional move instructions (MOVZ, MOVN)
- Atomic instructions of load-linked (LL) and store-conditional (SC)
- Cache instructions and line-based locking
