MIPS 24K

MIPS 24Kc / MIPS 24Kf

• Processor Identification: 00019374 (Processor ID: 0x93; Rev: 3.5.0)

The MIPS32 24K is a 8-stage pipeline processor core that implements the MIPS32 Release 2

Architecture, including support for dynamic branch prediction, optional MIPS DSP module,

MIPS16e Instruction Set Architecture and programmable L1 cache controller.

The 24K includes an OCP Bus Interface Unit, EJTAG debug and MIPS Trace support is provided.

The processor core delivers a performance of 1.6 DMIPS/MHz and 3.1 Coremarks/MHz.

The 24Kf version includes an IEEE754 compliant FPU, supporting both single and double precision datatypes.

Variants

• MIPS 24Kc is a 32-bit RISC core for high performance applications.
• MIPS 24Kc Pro core offers the CorExtend capability.

(CP0 Status Reg, Bit 17 set for CorExtend block)

• MIPS 24Kf core adds an IEEE-754 compliant floating point unit.

(CP0 Status Reg, Bit 29 set for Floating Point Unit)

• MIPS 24Kf Pro core has both the floating point unit

and the CorExtend capability.

ERRATA

Release Identifier	PRId [Revision] / Maj.min.patch/hex	Description	Date
2_0_*	2.0.0 / 0x40	General availability of 24K core.	March 19, 2004
3_0_*	3.0.0 / 0x60	COP2 option improvements.	September 30, 2004
3_2_*	3.2.0 / 0x68	PDtrace available.	March 18, 2005
3_4_*	3.4.0 / 0x6c	ISPRAM (I-side scratchpad) option added	June 30, 2005
3_5_*	3.5.0 / 0x74	8KB cache option	December 30, 2005
3_6_*	3.6.0 / 0x78	L2 support., 64KB alias-free D-cache option, option to have up to 8 outstanding cache misses (previous maximum 4).	July 12, 2006
3_7_*	3.7.0 / 0x7c	Less interlocks round cache instructions, relocatable reset exception vector location.	January 3, 2007
4_0_*	4.0.0 / 0x80	New UserLocal register, alias-proof I-cache hit-invalidate operation, can wait with interrupts disabled.	October 31, 2007
4_1_*	4.1.0 / 0x84	Errata fixes	January, 2009

See also

• MIPS32
• MIPS 24K
• MIPS 24Kc
• MIPS 24Kf
• MIPS 24KEc
• MIPS 24KEf